René Otten

Scaling up a quantum processor to tackle real-world problems requires qubit numbers in the millions. Scaleable semiconductor-based architectures have been proposed, many of them relying on integrated control instead of room-temperature electronics. However, it has not yet been shown that this can be achieved. For developing a high-density, low-cost wiring solution, it is highly advantageous for the electronics to be placed at the same temperature as the qubit chip. Therefore, tight integration of the qubit chip with ultra low power CMOS electronics presents a promising route. We demonstrate DC biasing qubit electrodes using a custom-designed 65nm CMOS capacitive DAC operating below 100mK [1]. Our chip features a complete proof of principle solution including interface, DAC memory and logic, the capacitive DAC, and sample-and-hold structures to provide voltages for multiple qubit gates. The bias DAC is combined with the qubit using a silicon interposer chip, enabling flexible routing and tight integration. Voltage stability, noise performance, and temperature are benchmarked using the qubit chip. Our results validate the potential of very low power qubit biasing using highly integrated circuits.

[1] P. Vliex et al., IEEE Solid-State Circuits Letters, vol. 3, pp. 218-221, 2020