Typically, spin-spin coupling in semiconductor qubits is short-range,which limits the scaling capabilities of QD-based architectures. Circuit QED can be a promising platform to solve this issue, since it allows to couplethe qubit state to microwave photons stored in superconducting resonators.
A way to improve the coupling between QD-qubits and microwave photons is to increase the impedance of the resonator. This can be realized using the kinetic inductance of Josephson junctions or disordered superconductors, such as NbN or granular Al.
Due to different requirements for substrate and design, combining semiconductor and superconductor technologies can be challenging. In this work, we explore the RF properties of different planar SiGe/Ge heterostructures, necessary for confining holes in QDs.
On the other side of this hybrid platform, the QDs are laterally defined by electrostatic gates. Metallic gates are patterned on a thin oxide layer deposited on the surface of the SiGe/Ge heterostructure. Generally, semiconductor-based devices suffer from low-frequency charge noise, mainly due to traps at the semiconductor-oxide interface. Under this prospective, it becomes fundamental to engineer a low-trap density interface. We study the trap density of metal-oxide-semiconductor (MOS) capacitors fabricated in different ways and on different substrates to identify the best fabrication recipe for low-charge noise dielectric for QDs.