With the advancement to more complex spin qubit devices and the employment of industrial CMOS technology for large scale fabrication, fast characterization of the fabricated devices becomes necessary. Furthermore, hysteresis effects have been observed in gate induced transport currents through the quantum well of a Si/SiGe heterostructure , which make measurements of SiGe QDs difficult.
Here, we present a concept to utilize DC measurements at 4 K for an automated inital characterization of devices used for shuttling of a single electron in a Si/SiGe quantum-channel . This concept improves the throughput of the inital quality control, which identifies devices with functional gates and a stable contact to the quantum well, by utilizing an automated measurement software. Our software performs gate functionality tests and trys to establish an SET without the need of manual input. Additionally, we focus on minimizing charge trapping during the measurement of devices, which is thought to be the cause of the hysteresis observed in the transport current. By employing a cautious approach with as low as possible voltages we find that 70% of measured SETs do not exhibit signatures of charge trapping. This approach also ensures that the maximum of data is collected from each device. Therfore, the fabrication yield of indivdual parts of the device can be determined and the time between device interations is reduced. Furthermore, this concept enables us to use the aggregated data to compare and evaluate different Si/SiGe heterostructures on which the devices are fabricated.
 A. Wild et al., Appl. Phys. Lett. 100, 143110 (2012).  I. Seidler et al., arXiv:2108.00879 (2021).