Silicon spin qubits have been considered as one of the most promising candidates for large scale quantum computers due to their long coherence times, potential to operate at relatively high temperatures, and compatibility with CMOS technology. However, the semiconductor / oxide interface has been widely identified as the source for charge noise and disorder sites, which limits the qubit performance and controllability.
We address this challenge by optimizing the whole gate stack with 300mm fabrication processes. On the fully integrated qubit structures, we characterize single electron transistors (SETs) across multiple devices at milli-Kelvin temperatures and report notably low levels of charge noise below 1 μeV/Hz. Moreover, the SET barriers show smooth pinch-off curves with highly uniform threshold voltages. These results underpin Si quantum dot qubit systems for large-scale quantum computing.