Alexander Willmes

Title of Poster
A scalable spin-shuttling architecture for Si/SiGe-based quantum computing
Abstract Regular

Universal quantum computing requires large numbers of physical qubits in order to correct errors using quantum error correction schemes like the surface code, which is known for its high error threshold of ~1% [1]. Si/SiGe spin-qubits recently achieved operational fidelities above this error threshold [2,3,4], shifting the focus to increasing qubit numbers. A viable architecture for quantum processor needs to provide solutions for scaling-up in two dimensions while providing enough space for control lines and potentially locally integrated control electronics. Here we present an architecture proposal that is entirely based on shuttling electrons over micron-scale distances [5,6] allowing for beyond next-neighbor coupling, low crosstalk, small operational frequencies and reduced magnetic field gradients, which leads to better coherence.
For this purpose we show detailed device simulations for the Si/SiGe platform of all relevant operations using realistic device parameters, provide estimates for operation fidelities and validate the producibility by providing realistic layouts compatible with state-of-the-art industrial fabrication technologies.
Assuming that electrons can be shuttled over several microns with high spin coherence, our architecture bridges the gap between conceptual propsals and device fabrication while optimizing operational performance, thus paving the way for a scalable Si/SiGe-based quantum processor.

[1] Fowler et al. Phys. Rev. A 86, 032324 (2012)
[2] Noiri et al. Nature 601, 338–342 (2022)
[3] Xue et al. Nature 601, 343–347 (2022)
[4] Mills et al. arXiv:2111.11937 (2021)
[5] Seidler et al. arXiv:2108.00879 (2021)
[6] Langrock et al. arXiv:2202.11793 (2022)

Poster Session